Provably good performance-driven global routing

نویسندگان

  • Jason Cong
  • Andrew B. Kahng
  • Gabriel Robins
  • Majid Sarrafzadeh
  • Chak-Kuen Wong
چکیده

We propose a provably good performance-driven global routing algorithm for both cell-based and building-block design. The approach is based on a new bounded-radius minimum routing tree formulation. We first present several heuristics with good performance, based on an analog of Prim's minimum spanning tree construction. Next, we give an algorithm which simultaneously minimizes both routing cost and the longest interconnection path, so that both are bounded by small constant factors away from optimal. This method is based on the following two results. First, for any given value of a parameter e, we can construct a routing tree with longest interconnection path length at most (I + e) R, and with cost at most (1 + (2/e)) times the minimum spanning tree weight. Moreover, for Steiner global routing in arbitrary weighted graphs, we achieve longest path length at most (1 + e) R, with wiring cost within a factor 2 . (1 + (2/e)) of the optimal Steiner tree cost. In both cases, R is the minimum possible length from the source to the furthest sink. We also show that geometry helps in routing: in the Manhattan plane, the total wire length for Steiner routing improves to 3/2 (1 + (I /e)) times the optimal Steiner tree cost, while in the Euclidean plane, the total cost is further reduced to (2/af3) ((I + (I /e)) times optimal. Furthermore, our method generalizes to the case where varying wire length bounds are prescribed for different source-sink paths. Extensive simulations confirm that this approach works well, using a large set of examples which reflect both cell-based and building-block layout styles.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

New Performance-Driven FPGA Routing Algorithms - Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Motivated by the goal of increasing the performance of FPGA-based designs, we propose new Steiner and arborescence FPGA routing algorithms. Our Steiner tree constructions significantly outperform the best known ones and have provably good performance bounds. Our arborescence heuristics produce routing solutions with optimal source–sink pathlengths, and with wirelength on par with the best exist...

متن کامل

A provably good multilayer topological planar routing algorithm in IC layout designs

Given a number of routing layers, the multilayer topological planar routing problem is to choose a maximum (weighted) set of nets so that each net in the set can be topologically routed entirely in one of the given layers without crossing other nets. This problem has important application in the layout design of multilayer IC technology, which has become available recently. In this paper, we pr...

متن کامل

Multicommodity Flow Algorithms for Buffered Global Routing

In this paper we describe a new algorithm for buffered global routing according to a prescribed buffer site map. Specifically, we describe a provably good multi-commodity flow based algorithm that finds a global routing minimizing buffer and wire congestion subject to given constraints on routing area (wirelength and number of buffers) and sink delays. Our algorithm allows computing the tradeof...

متن کامل

Competitive Routing of Virtual Circuits in ATM Networks

Classical routing and admission control strategies achieve provably good performance by relying on an assumption that the virtual circuits arrival pattern can be described by some a priori known probabilistic model. Recently a new online routing framework, based on the notion of competitive analysis, was proposed. This framework is geared towards design of strategies that have provably good per...

متن کامل

Provably good global buffering by generalized multiterminalmulticommodity flow approximation

To implement high-performance global interconnect without impacting the placement and performance of existing blocks, the use of buffer blocks is becoming increasingly popular in structured-custom and block-based ASIC methodologies. Recent works by Cong, Kong, and Pan [5] and Tang and Wong [21] give algorithms to solve the buffer block planning problem. In this paper, we address the problem of ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:
  • IEEE Trans. on CAD of Integrated Circuits and Systems

دوره 11  شماره 

صفحات  -

تاریخ انتشار 1992